The present invention relates to a semiconductor device and, particularly, to a semiconductor device with an SRAM (static random access memory) cell.
With the proliferation of mobile terminal equipment such as smartphones and the proliferation of in-vehicle microcomputers used for no-idling engines, automotive navigation systems or the like, the importance of SRAM (Static Random Access Memory) for processing high-volume digital signals at high speed is increasing today. Particularly, very high quality is required for in-vehicle microcomputers. Generally, high speed, small area and low power consumption are key features of SRAM.
In an SRAM memory cell array, cells for supplying a voltage to a well (well voltage supply cells) are arranged at specified intervals between memory cells. It is thus desirable that the size of the well voltage supply cells is small as well as the memory cells in order to reduce the area of SRAM.
It is also desirable that the well voltage supply cells are arranged with the same regularity as the surrounding memory cells in order to reduce fluctuations in characteristics and shape of transistors in the respective memory cells and enhance reliability.
It is further desirable to provide multiple power supplies in order to improve the low power consumption and the cell operating margin of the memory cells.
Japanese Unexamined Patent Application Publication No. 2001-28401 discloses a typical SRAM.
Japanese Unexamined Patent Application Publication No. 2007-305787 discloses SRAM in which stress on an isolation region is reduced.
Japanese Unexamined Patent Application Publication No. 2002-373946 discloses SRAM including well voltage supply cells that are arranged with the same regularity as the surrounding memory cells.
Japanese Unexamined Patent Application Publication No. 2007-43082 discloses SRAM provided with multiple power supplies.